Espressif Systems /ESP32-S2 /PMS /DMA_APB_I_1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DMA_APB_I_1

Description

Internal DMA permission control register 1.

Fields

DMA_APB_I_SRAM_0_R	Setting to 1 grants internal DMA permission to read SRAM Block 0.
DMA_APB_I_SRAM_0_W	Setting to 1 grants internal DMA permission to write SRAM Block 0.
DMA_APB_I_SRAM_1_R	Setting to 1 grants internal DMA permission to read SRAM Block 1.
DMA_APB_I_SRAM_1_W	Setting to 1 grants internal DMA permission to write SRAM Block 1.
DMA_APB_I_SRAM_2_R	Setting to 1 grants internal DMA permission to read SRAM Block 2.
DMA_APB_I_SRAM_2_W	Setting to 1 grants internal DMA permission to write SRAM Block 2.
DMA_APB_I_SRAM_3_R	Setting to 1 grants internal DMA permission to read SRAM Block 3.
DMA_APB_I_SRAM_3_W	Setting to 1 grants internal DMA permission to write SRAM Block 3.
DMA_APB_I_SRAM_4_SPLTADDR	Configure the split address of SRAM Block 4-21 for internal DMA access.
DMA_APB_I_SRAM_4_L_R	Setting to 1 grants internal DMA permission to read SRAM Block 4-21 low address region.
DMA_APB_I_SRAM_4_L_W	Setting to 1 grants internal DMA permission to write SRAM Block 4-21 low address region.
DMA_APB_I_SRAM_4_H_R	Setting to 1 grants internal DMA permission to read SRAM Block 4-21 high address region.
DMA_APB_I_SRAM_4_H_W	Setting to 1 grants internal DMA permission to write SRAM Block 4-21 high address region.

Links

() ()